1. Before the design of the design, it is necessary to think and determine the design strategy before the design starts, so as to guide the choice of element device, process selection, and circuit board production cost control. As far as SI is concerned, it is necessary to conduct a pre -investigation to form a planning or design criterion to ensure that the design results do not have obvious SI problems, skewers or timing issues.

     2. Some project teams of the circuit board have great autonomy to determine the number of PCB layers, but some other project teams do not have such autonomy. Therefore, it is important to understand your location. Other important issues include: What is the expected manufacturing tolerance? What is the expected insulation constant on the circuit board? What is the allowable error of line width and spacing? What is the allowable error of the thickness and spacing of the ground layer and the signal layer? All information can be used in the pre -wiring stage. According to the above data, you can choose layer stack. Note that almost every PCB inserted into other circuit boards or back panels has thickness requirements, and most circuit board manufacturers have a fixed thickness requirements for different types of layers they can manufacture. Essence You may want to work closely with the manufacturer to define the number of layers. The impedance control tool should be used to generate the target impedance range for different layers. It is necessary to take into account the impact of the manufacturers provided by the manufacturer and the effects of neighboring wiring. Under the ideal circumstances of the signal, all high -speed nodes should be wiring in the inner layer (such as band lines) in the impedance control. To make SI best and keep the circuit board coupled, the ground layer/power layer should be distributed as much as possible. If you can only have a pair of strata/power layers, you will only have it. If there is no power layer at all, you may encounter the SI problem according to the definition. You may also encounter such a situation, that is, it is difficult to simulate or simulate the performance of the circuit board before returning the path to the back path with an unabated signal.

     3. The coupling of string disturbance and impedance control from the neighboring signal line will cause string disturbance and change the impedance of the signal line. Coupling analysis of the adjacent parallel signal line may determine the "security" or expected spacing (or parallel wiring length) between the signal lines or between the signal lines. For example, if you want to limit the clock to the data signal node to within 100mV, you need to keep the signal wiring parallel, and you can find the minimum allowable spacing between the signal between any given wiring layer by calculating or simulation. At the same time, if the design contains important impedance nodes (or clocks or special high -speed memory architectures), you must place wiring on one (or several layers) to get the desired impedance.

     4. Important high -speed nodes delay and time lattice are key factor that must be considered by clock wiring. Because the timing requirements are strict, this node usually must use end -connecting devices to achieve the best SI quality. These nodes should be pre -determined, and the time required to adjust components and the time required to adjust the component to adjust the pointer of the signal integrity design.

     5. Technical selection of different driving technologies is suitable for different tasks. Is the signal point -to -point or a long tap? Is the signal output from the circuit board or stay on the same circuit board? What are the amount of time stagnation and noise that are allowed? As a common criterion for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for the 50MHz clock to rise with 500PS. The speed of a 2-3NS swing rate control device is fast enough to ensure the quality of the SI and help solve the problems such as the pitch output synchronous exchange (SSO) and electromagnetic compatibility (EMC). In the new FPGA programming technology or user definition ASIC, the superiority of driving technology can be found. With these customized (or semi -customized) devices, you have a lot of room to select the driving range and speed. In the early stage of design, it is necessary to meet the requirements of the FPGA (or ASIC) design time and determine the appropriate output option. If possible, it also includes pin selection. At this design stage, it is necessary to get a suitable simulation model from the IC supplier. In order to effectively cover SI simulation, you will need a Si simulation program and the corresponding simulation model (probably IBIS model). Finally, you should establish a series of design guidelines during the pre -wiring and wiring phase, including: target layer impedance, wiring spacing, device processes, important node topology and end -connecting planning.