Captive capacitors with appropriate capacity near the power pins of IC can make the IC output voltage jump faster. However, the problem is not here. Due to the characteristics of a limited frequency response, this makes the capacitance unable to generate the harmonic power required to drive the IC output on the full frequency band. In addition, the inductor ends of the transient voltage formed on the power supply flow discharge will form a voltage drop at both ends of the decoupled path. These transient voltage are the main co -mode EMI interference sources. How should we solve these problems?

     As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high -frequency capacitor. It can collect the energy leaked by the separate capacitors that provides high -frequency energy to clean output. In addition, the inductor layer of the excellent power layer is small, so the transient signal synthesized by the inductance is also small, thereby reducing the common model EMI.

     Of course, the connection of the power layer to the IC power pins must be as short as possible, because the rising edge of the digital signal is getting faster and faster.

     In order to control the co -mode EMI, the power layer should help decoupling and have enough inductances. This power layer must be a pairing of a very good power layer. Some people may ask, what extent is good? The answer to the question depends on the layers of the power supply, the materials between the layers, and the operating frequency (that is, the function of the IC rising time). Generally, the range of the power layer is 6mil, and the mezzanine is FR4 material, and the equivalent capacitance of each square inch power layer is about 75PF. Obviously, the smaller the laminar spacing, the larger the capacitance.

     There are not many devices with a rising time from 100 to 300ps, but according to the current development speed of ICs, devices rising from the range of 100 to 300ps will occupy a high proportion. For the circuit with 100 to 300PS rising time, the 3mil layer spacing will no longer be applicable to most applications. At that time, it was necessary to use a layered technology with a laminar spacing of less than 1mil, and the material with a high dielectric constant was replaced by the FR4 dielectric material. Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300PS rising time circuits.

     The co -model EMI can be reduced very low. The PCB layered stacking design instance given this article will assume that the laminar spacing is 3 to 6mil.