Pole (VIA) is one of the important parts of multi -layer PCB, and the cost of drilling usually accounts for 30%to 40%of the cost of PCB board. Simply put, every hole on the PCB can be called over -holes. From the perspective of effect, the holes can be divided into two categories:

     First, it is used as an electrical connection between each layer; the second is the fixation or positioning of the device. From the perspective of processes, these holes are generally divided into three categories, namely Blind Via, Buried Via, and Through Via. The blind hole is located on the top and bottom surface of the printing line board. It has a certain depth and is used for the connection of the surface line and the inner line below. The depth of the hole usually does not exceed a certain ratio (pore diameter). The buried hole refers to the connection hole located in the inner layer of the printing line board, which will not extend to the surface of the line board. The above two types of holes are located in the inner layer of the circuit board. Before the layer pressure, the through -hole molding process is completed. In the process of perforation, several inner layers may be overlapped. The third type is called Tongkou. This kind of holes pass through the entire line board and can be used to achieve internal interconnection or as component installation positioning holes. Because Tonghong is more easy to achieve in technology and low cost, most of the printing circuit boards use it instead of the other two types of perforated. If there is no special explanation mentioned below, all of the excessive holes are considered as a hole.

     From the perspective of design, a holes are mainly composed of two parts. One is the drilling of the middle (Drill Hole), and the other is the pad pad area around the drill. See the figure below. The size of these two parts determines the size of the holes. Obviously, when the high -speed and high -density PCB design, the designer always wants the smaller the hole, so that there can be more wiring space on the board. In addition, the smaller the holes, and the parasitic capacitance of its own own, and its own parasitic capacitance is also The smaller, the more suitable for high -speed circuits. However, the decrease in hole size has brought about increased costs, and the size of the perforated cannot be reduced without restrictions. The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilling hole, the hole wall cannot be evenly placed evenly. For example, the thickness of the 6 -layer PCB plate (through the hole depth) of the 6 -layer PCB plate is about 50mil, so the diameter diameter that PCB manufacturers can provide can only reach 8mil.

     Second, the parasitic capacitance of the perforated has a parasitic capacitor to the ground. The plate-based dielectric constant is ε, then the size of the parasitic capacitance of the perforated is similar to: C = 1.41εTD1/(D2-D1) Passion capacitance will cause the circuit to cause the circuit to prolong the rise of the signal and reduce The speed of the circuit. For example, for a PCB board with a thickness of 50mil, if the inner diameter is 10mil, the pad diameter is 20mil, and the distance between the pad and the copper area of the floor is 32mil, then we can use the above formula to calculate the perforated excessive excessive holes. The parasitic capacitor is roughly C = 1.41x4.4x0.050x0.020/(0.032-0.020) = 0.517pf. .517x (55/2) = 31.28ps. From these values, it can be seen that although the effect of rising and delay caused by a single perforated parasitic capacitor is not obvious, if the perforated over -the -hole switching between the traces is used multiple times in the wiring, the designer should consider it carefully.

     Third, the parasitic inductance of the perforated is also the same. There is a parasitic capacitor with parasitic capacitors at the same time. In the design of high -speed digital circuits, the harm of parasitic inductors of perforated is often greater than the effect of parasitic capacitors. Its parasitic series of inductors will weaken the contribution of bypass capacitors and weaken the filter effectiveness of the entire power system. We can use the following formula to simply calculate a parasitic inductance that is approximately perforated: l = 5.08h [ln (4h/d) +1] where L refers to the inductance of the perfunction, H is the length of the perfunction, D is the center of the center, D is the center Diamond diameter. It can be seen from the formula that the influence of the diameter of the perforated diameter has a small impact on the inductance, and the length of the perforated is more impact on the inductance. The above example still uses the above example. The inductance that can be calculated is: l = 5.08x0.050 [Ln (4x0.050/0.010) +1] = 1.015NH. If the signal is 1NS, the equivalent impedance size is: xl = πl/T10-90 = 3.19Ω. Such impedance can no longer be ignored in the passing of high -frequency current. In particular, it is necessary to note that by the connection of the power layer and the strata, two perforated perforated, so that the parasitic inductance of the perforated is doubled.